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Clock Generators for SOC Processors : Circuits and Architectures download torrent

Clock Generators for SOC Processors : Circuits and Architectures download torrent

Clock Generators for SOC Processors : Circuits and Architectures.cAmr M. Fahim
Clock Generators for SOC Processors : Circuits and Architectures
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Author: Amr M. Fahim
Page Count: 264 pages
Published Date: 05 Nov 2010
Publisher: Springer-Verlag New York Inc.
Publication Country: New York, NY, United States
Language: English
ISBN: 9781441954701
File size: 45 Mb
File Name: Clock.Generators.for.SOC.Processors.Circuits.and.Architectures.pdf
Download Link: Clock Generators for SOC Processors Circuits and Architectures
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This book examines the issue of design of fully integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discre- time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The material then develops into detailed circuit and architectural analysis of specific clock generation blocks. This includes circuits and architectures of PLLs with high power supply noise immunity and digital PLL architectures where the loop filter is digitized. Methods of generating low-spurious sampling clocks for discrete-time analog blocks are then examined. This includes sigma-delta fractional-N PLLs, Direct Digital Synthesis (DDS) techniques and non-conventional uses of PLLs. Design for test (DFT) issues as they arise in PLLs are then discussed. This includes methods of accurately measuring jitter and built-in-self-test (BIST) techniques for PLLs.

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